FIG. 7 is an equivalent circuit diagram illustrating a semiconductor integrated circuit (hereinafter referred to as IC) of a single-stage amplifier using a conventional gate bias circuit. In the figure, reference numeral 1 designates a field effect transistor (hereinafter referred to as FET), numeral 2 designates a signal input terminal, and numeral 3 designates a capacitor. An input end of the capacitor 3 is connected to the signal input terminal 2 and an output end of the capacitor 3 is connected to a gate of the FET 1. Reference numeral 10 designates a ground plane, numerals 112 and 113 designate resistors R.sub.12 and R.sub.13, respectively, and numeral 114 designates a gate bias terminal. An end of the resistor R.sub.12 is connected to the output end of the capacitor 3 and to the gate of the FET 1 while the other end is connected to the gate bias terminal 114. An end of the resistor R.sub.13 is connected to the output end of the capacitor 3 and to the gate of the FET 1 while the other end is connected to the ground plane 10. Reference numerals 21 and 22 designates first and second transmission lines, respectively, each serving as an output matching circuit. These transmission lines 21 and 22 are microstrip lines or coplanar lines formed on the IC. Reference numeral 23 designates an inductor which is formed by patterning a metal thin film having a prescribed width in spiral shape or meandering line shape. Reference numerals 24 and 25 designate capacitors, numeral 26 designates a drain bias terminal, and numeral 27 designates a signal output terminal.
FIG. 9 is a sectional view of the FET 1 included in the single-stage amplifier of FIG. 7. In the figure, reference numeral 31 designates a GaAs substrate. The FET includes a gate electrode 33 comprising tungsten silicide (WSi), a source electrode 36, and a drain electrode 37. The source and drain electrodes 36 and 37 comprise AuGe. An n type active region 32 is disposed within the substrate 31 and lies at a surface where the gate electrode 33 is disposed. Relatively heavily doped n.sup.+ type source and drain regions 34 and 35 are disposed within the substrate 31 lying below the source and drain electrodes 36 and 37, respectively. In production, the n type active region 32 is formed by implanting n type impurity ions, such as Si ions, into the substrate 31. Then, the center portion of the n type region is masked and the n.sup.+ type source and drain regions 34 and 35 are formed by heavily implanting the n type impurity ions.
A description is given of the operation.
A radiofrequency signal (hereinafter referred to as RF signal) which is input to the signal input terminal 2 is transmitted through the capacitor 3 to the gate of the FET 1. A partial voltage V.sub.g1, which is determined by a voltage V.sub.g0 applied to the gate bias terminal 114 and by the resistors R.sub.12 and R.sub.13 according to the following equation (1), is applied to the gate of the FET 1 as a gate voltage. EQU V.sub.g1 =V.sub.g0 (R.sub.13 /(R.sub.12 +R.sub.13)) (1)
Further, a drain voltage V.sub.dd is applied to the drain of the FET 1 from the drain bias terminal 26. Therefore, a drain current I.sub.d1, which is determined by the drain voltage V.sub.dd the gate voltage V.sub.g1, and the DC characteristic of the FET 1, flows between the source and the drain of the FET 1, whereby the RF signal in the gate of the FET 1 is amplified, and the amplified RF signal is transmitted through the first and second transmission lines 21 and 22 and the capacitor 25 and output from the signal output terminal 27.
FIG. 8 illustrates DC characteristics between the drain current I.sub.d and the gate voltage V.sub.g of the FET 1. A drain current I.sub.d1 of the FET 1 is determined by the threshold voltage V.sub.th of the FET 1, the gain coefficient K, and the gate voltage V.sub.g1 according to the following equation
(2). EQU I.sub.d1 =K(V.sub.g1 -V.sub.th).sup.2 ( 2)
In the gate bias circuit shown in FIG. 7, the gate voltage V.sub.g1 of the equation (2) is a fixed gate voltage determined by the equation (1), so that the above-described amplification is carried out with the drain current I.sub.d1 according to the equations (1) and (2).
In the above-described gate bias circuit of the conventional semiconductor IC, the gate voltage V.sub.g1 applied to the gate electrode of the FET 1 is fixed if the voltage V.sub.g0 applied to the gate bias terminal 114 is constant. In the conventional semiconductor IC, however, it is impossible to fabricate a plurality of FETs 1 with uniform impurity dopant concentration and uniform thickness of the n type active layer 32 and uniform length of the gate electrode 33 from wafer to wafer or from lot to lot, so that the threshold voltage V.sub.th and the gain coefficient K in the equation (2), i.e., I.sub.d1 =K (V.sub.g1 -V.sub.th).sup.2, undesirably vary between devices, resulting in undesirable differences in the drain current I.sub.d between devices. In this case, as shown in FIG. 8, although the amplifier FET 1 is designed to have an operating point Q with the DC characteristic shown by the continuous line, the operating point unfavorably shifts to Q1 or Q2 if the DC profile varies as shown by the broken line (a) or (b), respectively resulting in undesirable variations in high frequency characteristics, such as input-output characteristics, from chip to chip.